1 of 6 111799 features all-silicon pulse width generator five programmable widths equal and unequal incr ements available pulse widths from 5 ns to 500 ns widths are stable and precise rising edge-triggered inverted and non-inverted outputs width tolerance 5% or 2 ns, whichever is greater economical auto-insertable, low profile low-power cmos ttl/cmos-compatible vapor phase, ir and wave solderable custom widths available fast turn prototypes extended temperature range available pin assignment pin description in C trigger input p0-p2 C programming pins gnd C ground out C pulse output out C inverted pulse output v cc C +5v description the ds1040 pulse generator is a user-programmable one-s hot with a choice of fi ve precise pulse widths. maximum widths range from 50 ns to 500 ns; increments range from 2.5 ns to 100 ns. for maximum flexibility in applications such as magneto-optical read/write disk laser power control, varieties are offered with equal and un equal increments. the ds1040 is offere d in standard 8-pin dips and 8-pin mini-soics. low cost and superior reliability over hybrid technology are achieved by the combination of a 100% cmos silicon design and industry standard packaging. the ds1040 series of pulse generators provide a nominal width accuracy of 5% or 2 ns, whichever is greater. in response to the rising edge of the input (trigger) pulse, the ds 1040 produces an output pulse with a width determined by the logic states of the three parallel programming pins. fo r convenience, both inverting and non-inverting outputs are supplied. the intrinsic delay between the trigger pulse and the output pulse is no more than 10 ns. each output is capable of driving up to five 74ls loads. dallas semiconductor can customize sta ndard products to meet special n eeds. for special request and rapid delivery, call (972) 371C4348. ds1040 programmable one-shot pulse generato r www.dalsemi.com ds1040z 8-pin soic (150-mil) see mech. drawings section in out out gnd v cc p2 p0p1 1 2 3 4 8 7 6 5 ds1040m 8-pin dip (300-mil) see mech. drawings section v cc p2 p0p1 in out out gnd 1 2 3 4 8 7 6 5 downloaded from: http:///
ds1040 2 of 6 logic diagram figure 1 pulse width vs. programmed value table 1 programming pins max width min width max width max width max width msb p2 0 0 0 0 1 1 1 1 p1 0 0 1 1 0 0 1 1 lsb p0 0 1 0 1 0 1 0 1 part number ds1040-75 75 15 30 45 60 75 75 75 ds1040-100 100 20 40 60 80 100 100 100 ds1040-150 150 30 60 90 120 150 150 150 ds1040-200 200 40 80 120 160 200 200 200 ds1040-250 250 50 100 150 200 250 250 250 ds1040-500 500 100 200 300 400 500 500 500 ds1040-b50 50 30 35 40 45 50 50 50 ds1040-d60 60 20 30 40 50 60 60 60 ds1040-a15 15 5 7.5 10 12.5 15 15 15 ds1040-a20 20 10 12.5 15 17.5 20 20 20 ds1040-a32 32.5 22.5 25 27.5 30 32.5 32.5 32.5 ds1040-b40 40 20 25 30 35 40 40 40 ds1040-d70 70 30 40 50 60 70 70 70 all times in nanoseconds.custom pulse widths available. downloaded from: http:///
ds1040 3 of 6 absolute maximum ratings* voltage on any pin relativ e to ground -1.0v to +7.0v operating temperature 0 c to 70 c storage temperature -55 c to +125 c soldering temperature 260 c for 10 seconds short circuit output current 50 ma for 1 second * this is a stress rating only and f unctional operation of the device at th ese or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. dc electrical characteristics (0c to 70c; v cc = 5.0v 5%) parameter symbol test min typ max units notes supply voltage v cc 4.75 5.00 5.25 v 1 high level input voltage v ih 2.2 v cc + 0.5 v1 low level input voltage v il -0.5 0.8 v 1 input leakage current i i 0.0 v i v cc -1.0 1.0 a active current i cc v cc = max; period = min 35 75 ma 2, 6 high level output current i oh v cc = min v oh = 4 -1 ma low level output current i ol v cc = min v ol = 0.5 8m a ac electrical characteristics (t a = 25c; v cc = 5.0v 5%) parameter symbol min typ max units notes programming setup t ps 5n s programming hold t ph 0n s input pulse width at logic 1 t wih 5n s input pulse width at logic 0 t wil 5n s intrinsic delay t d 0 5 10 ns output pulse width t wo table 1 ns 3, 4, 5, 7 power-up time t pu 100 ms period period t wo + 50 ns capacitance (t a = 25c) parameter symbol min typ max units notes input capacitance c in 51 0p f downloaded from: http:///
ds1040 4 of 6 notes:1. all voltages are referenced to ground. 2. measured with outputs open, minimum period. 3. v cc = 5v @ 25 c. width accurate to within 2 ns or 5%. 4. temperature variations between 0 c and 70 c may increase or decrease width by an additional 1 ns or 3%, whichever is greater. 5. for ds1040 pulse generators with maximum widths less than 50 ns, temperature variations between 0 c and 70 c may increase or decrease width by 1 ns or 9%, whichever is greater. 6. i cc is a function of frequency a nd maximum width. only a pulse generator operating with 40 ns period and v cc =5.25v will have an i cc =75 ma. for example, a -100 will never exceed 30 ma, etc. 7. see test conditions sections at the end of this data sheet. timing diagram figure 2 downloaded from: http:///
ds1040 5 of 6 power-up timing diagram figure 3 test circuit figure 4 terminologyperiod: the time elapsed between the leading edge of the first trigger pulse and the leading edge of the following trigger pulse. t wih , wil , wo (pulse width): the elapsed time on the pulse between the 1.5v point on the leading edge and the 1.5v point on the trailing edge, or the 1.5v point on the trailing edge and the 1.5v point on the leading edge. downloaded from: http:///
ds1040 6 of 6 t rise (input rise time): the elapsed time between the 20% and the 80% point on the leading edge of the input pulse.t fall (input fall time): the elapsed time between the 80% and the 20% point on the trailing edge of the input pulse.t d (intrinsic delay): the elapsed time between the 1.5 point on th e leading edge of the input trigger pulse and the 1.5v point on the leading edge of output pulse. t pu (power-up time): after v cc is valid, the time required before timing specifications is within tolerance. test setup description figure 4 illustrates the hardware configuration used for measuring the timing parameters on the ds1040. the input waveform is produced by a precision pulse generator under software control. the intrinsic delay is measured by a time interval counter (20 ps resolution) connected between the input and each output. outputs are selected and connected to the counter by a vhf switch control unit. width measurements are made by directing both the st art and stop functions of the counter to the same output. all measurements are fully automated, with each instrument controlled by a central computer over an ieee 488 bus. test conditions input: ambient temperature: 25 c + 3 c supply voltage (v cc ): 5.0v + 0.1v input pulse: high = 3.0v + 0.1v low = 0.0v + 0.1 source impedance: 50 ohm max. rise and fall time: 3.0 ns max. (measured between 0.6v and 2.4) pulse width: 500 ns (1 s for -500) period: 1 s (2 s for -500) output: the output is loaded with a 74f04. delay is measur ed at the 1.5v level on the rising and falling edge. note: above conditions are for test only and do not restrict the operation of the device under other data sheet conditions. downloaded from: http:///
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